SK hynix answers with "memory-centric" at OCP 2026: CXL memory pooling, the MARS rack and CMM-Ax

The memory wall and one judgment

From October 12 to 15, OCP Global Summit 2026 took place in San Jose, California. OCP is a technical conference for sharing and standardizing data center hardware design and specifications, and this year one of its central themes was the infrastructure technology that keeps AI moving forward. SK hynix gave over a large part of its booth to system-level demonstrations — not chips behind glass, but next-generation memory designs running inside real systems.

The company's judgment fits in one sentence: memory-centric server systems are the future. The backdrop is explosive growth in the volume of data AI handles, which has made data bottlenecks a new problem: existing architectures centered on CPUs and GPUs have hit the memory wall, and power consumption is climbing along with them. SK hynix's answer is to put memory at the center of the system instead of keeping it in a supporting role.

Memory as a pool: CMM-DDR5 and CXL

Three solutions were lined up from left to right in the demo area: CMM-DDR5, MARS and CMM-Ax. CMM stands for CXL Memory Module; the idea is to let multiple servers share one memory pool and take as much as they need, improving resource utilization. CXL itself is an interconnect standard based on PCIe that links CPUs, GPUs and memory efficiently and adds pooling capability.

What was shown is the second-generation CMM-DDR5: 256 GB, based on CXL 3.2 and optimized for AI workloads. Compared with the previous generation it more than doubles bandwidth (80 GB/s), improves energy efficiency by about 30%, and adds CXL Pooled functionality. For data-intensive, high-load environments, such products are expected to ease the memory bottleneck.

This is not the technology's first outing. SK hynix signed a business agreement with NAVER Cloud in September last year and has since worked on relieving bottlenecks in cloud AI services with CXL-based memory. At this demo the company presented proof-of-concept results: whether sharing a KV cache in an agentic AI environment, and sharing embeddings in the omni-modal service OmniServe, actually works. KV cache is the temporary memory that stores results an LLM-based agent has already computed; the longer the conversation and the more tasks involved, the faster it grows — so how it is stored and retrieved directly affects an agent's performance.

MARS: a rack built around memory

MARS stands for Memory Centric AI Rack System. Its approach is to integrate partners' solutions into a single rack with memory at the core. SK hynix ran three demos together with partners.

The first was an agentic AI serving demo with Arcee, Liqid and Marvell: pooled memory connects multiple servers and GPUs, demonstrating that transferring or reusing a KV cache over CXL pooled memory improves system performance significantly compared with conventional methods that rely on network communication.

The second, with AMD, Penguin, Xcena and Arcee, validated a memory rack using both CXL memory and CXL hybrid memory (DRAM plus SSD) for storing and rapidly reusing the large-scale KV caches that are continuously generated. Two capabilities stood out: predicting which KV caches will be needed from prior conversation and task history, and preloading them into DRAM for faster processing. Storing the full KV cache on SSD then delivers both fast reads and high capacity at the same time.

The third demo, with personal AI agent provider Pickle, used pooled memory to cut service response latency. A personal agent has to string multiple AI models together, and SK hynix showed that pooled-memory streaming can accelerate data movement between those models so results reach users sooner.

Hosik Kim, the vice president who heads the Memory Systems Research department, put it plainly in his talk: the system implements rack-level memory pooling and dynamic zero-copy data sharing by connecting CPUs and GPUs with next-generation CXL technology, and is structured to significantly increase the speed of data movement in high-load workloads. He named three beneficiaries: KV cache reuse efficiency for collaborative agentic AI, response speed for multimodal omni models in personal agent services, and the irregular memory access problems that arise in large-scale graph neural network training.

CMM-Ax computes inside memory — plus two HBM and HBF product lines

The third solution, CMM-Ax, takes a different road: it combines computation with memory so that computation happens inside the memory without moving data, reducing the power and cost burden on data centers. At the booth SK hynix demonstrated it with a next-generation AI inference system called Efficient Long Context LLM Serving, showing that CMM-Ax can efficiently accelerate long contexts that conventional GPU-based systems struggle with. The research behind it was recognized for technical excellence and published at MICRO 2026, the most prestigious academic conference in computer architecture.

There were more detailed engineering talks around this. Jongryool Kim, team leader of AI System Infra, described shared-memory technologies that raise agentic AI service performance: token sharing accelerates CPU-based tokenization, KV cache sharing improves response speed and resource efficiency, and tokenization plus real-time KV cache importance analysis can be offloaded to computational shared memory. Younghoon Min, working with Professor Kiwan Maeng of Pennsylvania State University, spoke on using computational memory to make differentially private training more efficient. Juhee Lee of AI Platform SW shared storage as a performance tier for LLM serving. A separate panel discussed integrating software frameworks and APIs across companies for PIM and PNM, and the need for standardization there.

The other half of the booth was products. The eSSD lineup was arranged by form factor: the high-performance PS1010 U.2; the high-performance PS1110 E3.S and high-capacity PS1101 E3.S in sequential development; and the PEB210 E1.S and PEB210 M.2 2280, which support direct liquid cooling. On the server DRAM side, capacities ran from the 256GB 3DS RDIMM, which the company calls the industry's largest capacity for AI workloads, down to 96GB and 64GB, alongside a 128GB DDR5 MRDIMM and a 192GB SOCAMM2 that improves power and space efficiency with a new form factor.

The HBM display sat at the center: on one side a model of NVIDIA's Vera Rubin superchip, where visitors could mount HBM4 and SOCAMM2 onto a server model themselves; on the other a model of HBM magnified a million times next to a screen explaining TSV and Advanced MR-MUF; in between the actual HBM4E, HBM4 and HBM3 products, so the generational progression is visible at a glance. The official sequence runs HBM, HBM2, HBM2E, HBM3, HBM3E, HBM4 and HBM4E. Advanced MR-MUF is described as applying warpage control to stack chips 40% thinner than conventional ones without bending, while also improving heat dissipation. SK hynix also introduced HBF (High Bandwidth Flash), which applies TSV technology as HBM does to combine the capacity of conventional storage with high bandwidth; its internal simulations show HBM suits scenarios that need fast response, while HBF suits those that need large capacity to serve many users. The company's summary of the summit: the meaningful part this year was being able to show how next-generation memory solutions work in real systems.