Espressif unveils the ESP32-S31: dual-core 320 MHz RISC-V with Wi-Fi 6

On March 26, Espressif announced the ESP32-S31, describing it as its most capable SoC yet: dual-core 32-bit RISC-V running at up to 320 MHz with MMU support. It still belongs to the ESP32 family, but it has clearly moved up a tier — aimed not just at connected sensors but at complete human-machine interfaces with a display, a camera and audio. Official target scenarios include smart appliances, smart speakers, voice-controlled devices, smart-home hubs, industrial automation systems and multimedia IoT applications.

Connectivity is the headline: 2.4 GHz Wi-Fi 6 (802.11ax); Bluetooth 5.4 with both Classic (BR/EDR) and LE Audio, plus direction finding and Bluetooth Mesh 1.1; an IEEE 802.15.4 radio carrying Thread and Zigbee; and a 1000 Mbps Ethernet MAC. Espressif notes that Matter support spans both the Wi-Fi and Thread paths — in other words, the most common ways for IoT devices to connect now sit on a single piece of silicon.

One chip, several ways to connect

Putting several wireless and wired paths in one SoC means a device’s form factor is no longer dictated by how it connects. Wi-Fi 6’s gains land mainly in transmission efficiency and power in dense environments: more devices can share the same space, and battery-powered units can save energy through smarter wake-up mechanisms — which matters most where devices pile up, as in a smart home. Note, though, that the S31’s Wi-Fi 6 covers only the 2.4 GHz band, not 5 GHz or 6 GHz. If a product needs 5 GHz bandwidth or the clean spectrum at 6 GHz, it has to add a Wi-Fi 6E co-processor — and Espressif’s own E22 fills exactly that slot.

On the Bluetooth side, LE Audio handles high-quality, low-power streaming while direction finding serves precise-location applications; Classic (BR/EDR) keeps compatibility with existing audio gear and legacy use cases needing low latency and high throughput. Coexistence algorithms coordinate the two radios when both run. The IEEE 802.15.4 path is for low-power mesh networking, carrying Thread or Zigbee, and the 1000 Mbps Ethernet MAC offers a wired option when stable high bandwidth is required.

Having many protocols side by side raises a product question: which link should a device actually use? Wi-Fi carries bandwidth, Thread handles low-power mesh, Bluetooth covers provisioning and audio, Ethernet provides stable backhaul. Leaving that choice to the product definition is far more flexible than forcing designers to lock in a protocol at component-selection time — one board can switch networking mode by scenario without a hardware redesign.

Displays and cameras: HMI is the focus of this generation

The real dividing line is the multimedia interfaces. The ESP32-S31 provides an 8- to 16-bit DVP camera interface, an 8- to 24-bit parallel LCD interface with hardware colour-space conversion, and up to 14 capacitive touch channels. That set is close to what an HMI host controller offers: screen, touch and camera can all hang off the main chip, removing a separate display controller and the debugging work of yet another link. For a display-equipped product, one less part on the bill of materials often beats another few dozen megahertz on the spec sheet.

To make those workloads fly, dedicated accelerators are built in: JPEG encode/decode, PPA-based 2D graphics acceleration and 2D-DMA for image processing and display refresh. On audio there are dual I2S controllers plus hardware-level Bluetooth audio synchronisation — handing timing alignment to hardware removes the jitter and complexity of software synchronisation, which is very practical for voice-interaction and playback devices.

On compute, one core has a 128-bit-wide data path with SIMD instructions for parallel processing; memory is 512 KB of SRAM plus 250 MHz 8-bit DDR PSRAM with concurrent Flash and PSRAM access. With dedicated interfaces supporting up to Octal SPI, the chip clearly targets memory-hungry multimedia and edge AI workloads. It provides 60 GPIOs, leaving plenty of room for peripherals. The value of SIMD with a 128-bit data path shows up most in regular data such as images and audio: more data moved per clock. DDR PSRAM, meanwhile, decides whether a whole frame fits in memory or has to be shuffled in blocks.

Security and isolation move to the foreground

Security is generously specified this generation: RAM-based PUF for key management, secure boot, Flash and PSRAM encryption, a digital signature peripheral, cryptographic hardware acceleration, and protection against side-channel attacks and power glitches. A trusted execution environment (TEE) with access permission management (APM) provides software isolation for secure multi-application deployment — in plain terms, letting code from different sources each occupy its own room. For connected devices, security has moved from a bonus to a ticket for entry. Chip support is only the precondition, though: whether that security really works depends on the vendor enabling the switches and storing keys correctly.

Peripherals include USB OTG (high speed), TWAI (CAN 2.0 compatible) and the usual I2C, I2S, SPI, UART, LED PWM, ADC, SDIO, timers and DMA. Software support comes from ESP-IDF, ESP-Matter and the multimedia-oriented ESP-GMF; through the ESP-Hosted and ESP-AT frameworks it can also serve as a connectivity co-processor rather than only as the host — a dual role that helps product lines get reused. For teams already on ESP-IDF, migration cost concentrates on the new multimedia and display interfaces.

Schedule and roadmap

On timing, official information puts customer sampling in May 2026 and mass production in July; interested customers can contact Espressif’s sales support for samples. Espressif also links the S31 to its ESP Private Agents platform and to working directly with common large models, pointing at voice-interaction client devices. For developers the schedule matters more than the spec sheet: sampling in May and production in July leaves only a few months for board design and software porting.

Widening the timeline helps: in January 2026 Espressif announced the ESP32-E22 (its first Wi-Fi 6E connectivity co-processor); in March it followed with the ESP32-H21 (low-power Thread/BLE, 96 MHz RISC-V) and then the S31. The company is also developing a higher-performance edge AI chip based on its in-house RISC-V, reported by foreign media to use 12 nm, with no detailed specifications yet.

That sketches a shift in competitive position. Espressif’s products used to be compared mainly with each other — C3 versus C6 as an upgrade path — but the S31’s specification (dual 320 MHz cores, DDR PSRAM, LCD and camera interfaces, a TEE) now sits in application-processor territory, and customers may weigh it against entirely different chips. Whether it holds that position depends on production pricing, ecosystem maturity and developers’ willingness to migrate.

The conclusion can be put plainly: Espressif is using RISC-V to push from low-power wireless all the way to display-equipped HMI and edge AI. On paper at least, this is no longer a networking MCU so much as a multimedia application processor with wireless built in. Whether the specification delivers will be answered by customer designs after mass production starts in July 2026.